GaN-based high electron mobility transistor and method for making the same

ABSTRACT

A high electron mobility transistor including: a GaN material system based heterostructure; a passivating nitride layer over the heterostructure and defining a plurality of openings; and a plurality of electrical contacts for the heterostructure and formed through the openings.

FIELD OF INVENTION

The present invention relates generally to transistors, and moreparticularly, to GaN based High Electron Mobility Transistors (HEMTs)and methods for making such transistors.

BACKGROUND

High Electron Mobility Transistors are known to be desirable in certainapplications. One such application is microwave amplifiers. They areknown to generally yield higher output power densities, lower noisefigures, and be able to operate at higher frequencies as compared toother Field Effect Transistors (FETs). GaN material system based HEMT'sare believed to be desirable for use in Radio Frequency (RF) modulationschemes and interfaces.

However, drain current reduction at high frequencies has conventionallylimited the available output power in GaN material system-based HEMTdevices, which is believed to be caused by the surface states. It isbelieved desirable to passivate the surface states and prevent surfacedamage during device processing. Low breakdown voltage hasconventionally limited high drain biases for GaN material system basedHEMT devices. It is believed desirable to increase the breakdownvoltage. Further, the power performance of conventional GaN materialsystem based HEMT devices typically degrades at high junctiontemperatures, due to reduced carrier saturation velocity and increasedparasitic resistance. It is believed to be desirable to maintain a hightwo dimensional electron gas (2DEG) mobility even at high temperatures.Repeatable low contact resistance in conventional GaN material systembased HEMT devices has also proven problematic for high frequencyoperation. It is believed desirable to provide for repeatable and lowcontact resistances. It is also believed to be desirable to increase the2DEG sheet charge and maintain 2DEG confinement to increase usable RFpower and eliminate drain current reduction at high frequencies.

SUMMARY OF THE INVENTION

A high electron mobility transistor including: a GaN material systembased heterostructure; barrier surface protection during MESAprocessing; a front end passivating dielectric layer over theheterostructure and defining a plurality of low damage etch processedopenings for electrical ohmic contacts for source and drain electrodesand for Schottky contacts for gate electrodes on the heterostructurethrough the openings; ohmic contact opening surface treatments andsource/drain ion implantation to reduce contact and source/drainresistance; and a double heterostructure for improved carrierconfinement.

According to an aspect of the present invention, a method for making ahigh electron mobility transistor includes low pressure chemical vapordepositing a passivating nitride layer over a GaN material system basedheterostructure; etching openings in the nitride layer; and formingelectrodes through the openings.

BRIEF DESCRIPTION OF THE DRAWINGS

Understanding of the present invention will be facilitated byconsidering the following detailed description of the preferredembodiments of the present invention taken in conjunction with theaccompanying drawings, in which like numerals refer to like parts, and:

FIG. 1 illustrates a diagrammatic view of a HEMT;

FIG. 2 illustrates a diagrammatic view of a HEMT according to an aspectof the present invention;

FIG. 3 illustrates a diagrammatic view of a HEMT according to an aspectof the present invention;

FIG. 4 illustrates a diagrammatic view of a HEMT according to an aspectof the present invention;

FIG. 5 illustrates a diagrammatic view of a HEMT according to an aspectof the present invention;

FIG. 6 illustrates a diagrammatic view of a HEMT according to an aspectof the present invention;

FIG. 7 illustrates performance characteristics according to an aspect ofthe present invention;

FIG. 8 illustrates a diagrammatic view of a HEMT according to an aspectof the present invention;

FIGS. 9A-9D illustrate diagrammatic views of an AlGaN/GaNheterostructure during different processing steps according to an aspectof the present invention;

FIGS. 10A-10C illustrate diagrammatic views of an AlGaN/GaNheterostructure during different processing steps according to an aspectof the present invention;

FIGS. 11A-11E illustrate diagrammatic views of an AlGaN/GaNheterostructure during different processing steps according to an aspectof the present invention; and

FIGS. 12A-12D illustrate diagrammatic views of an AlGaN/GaNheterostructure during different processing steps according to an aspectof the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

It is to be understood that the figures and descriptions of the presentinvention have been simplified to illustrate elements that are relevantfor a clear understanding of the present invention, while eliminating,for the purpose of clarity, many other elements found in typicaltransistor systems and processing methods. Those of ordinary skill inthe art may recognize that other elements and/or steps are desirableand/or required in implementing the present invention. However, becausesuch elements and steps are well known in the art, and because they donot facilitate a better understanding of the present invention, adiscussion of such elements and steps is not provided herein.

Referring now to FIG. 1, there is shown a diagrammatic view of a HighElectron Mobility Transistor (HEMT) device 10. Device 10 generallyincludes a substrate 20, an optional nucleation layer 30, buffer layer40, barrier layer 50, 2DEG region 60, and passivation layer 70. Device10 also includes a T-gate 80, source 90 and drain 100. T-gate 80 may belaterally off-set towards source 90. For example, the lateral separationbetween T-gate 80 and source 90 may be on the order of about 0.5-2 μm(micrometer), preferably about 1 μm, while the lateral separationbetween T-gate 80 and drain 100 may be on the order of about 1-5 μm, andpreferably about 2 μm.

Substrate 20 may take the form of a semi-insulating monocrystallinesilicon carbide (SiC) substrate. SiC substrate 20 may be of a 4H or 6Hpolytype, for example. Substrate 20 may also take the form of asemi-insulating monocrystalline bulk GaN substrate, or may take the formof a sapphire substrate, or a semi-insulating monocrystalline AlNsubstrate, all by way of non-limiting example.

Nucleation layer 30 may take the form of an AlN, or a GaN, or an AlGaNlayer; preferably a low-temperature AlN, nucleation layer where a 4H or6H-SiC or sapphire substrate 20 is used. Nucleation layer 30 mayoptionally be omitted where substrate 20 takes the form of a bulk GaN orAlN substrate, for example.

Buffer layer 40 may take the form of a resistive GaN layer. Barrierlayer 50 may take the form of an AlGaN layer. AlGaN barrier layer 50 maybe Si doped or undoped, and preferably is undoped. Channel 60 representsa 2-dimensional electron gas (2DEG) channel formed by the heterojunctionbetween buffer layer 40 and barrier layer 50. The heterostructure maytake the form of an AlGaN/GaN, or AlN/GaN heterostructure. A2-Dimensional Electron Gas (2DEG) forms at the interface between bufferlayer 40 and barrier layer 50, i.e., channel 60, as a result of wellknown strong spontaneous polarization and piezoelectric polarizationeffects in GaN-based material systems. The resulting high density, highmobility AlGaN/GaN 2DEG may be used to provide HEMT functionality whenmodulated by gate electrode 80.

Passivation layer 70 may take a conventional form where low temperature(400 deg. C.) plasma enhanced chemical vapor deposition (PECVD)passivation material is deposited after high temperature ohmic contactannealing and overlay and gate metallization processing have beencompleted. For example, passivation layer 70 may take the form of asurface film including SiN_(x), AlN, Sc₂O₃, MgO or SiO₂.

Ohmic contacts/overlay metallization processing may be used to formsource and drain electrodes 90, 100. Schottky metallization may be usedto form T-gate electrode 80.

Referring now also to FIG. 2, there is shown a diagrammatic view of a“front end” field plate-type surface passivated High Electron MobilityTransistor (HEMT) device 200 according to an aspect of the presentinvention. Like numerals refer to like elements of the invention. Fieldplate-type passivation layer 210 provides for better surface coverage inregions 110 than does conventional passivation layer 70 because it isdeposited early in the processing. This allows for stabilization ofsurface states in region 110. The extended passivation layer 210 underT-gate 80 may also provide for increased breakdown voltage as comparedto passivation layer 70, by spreading the crowded electric field andmodulating the surface states on the drain 100 side around T-gate 80.

According to an aspect of the present invention, a passivation layer,such as passivation layer 210, may be deposited relatively early duringdevice processing. Passivation may occur prior to ohmic source or drainterminal contact, and gate formation. According to an aspect of thepresent invention, a passivation layer, such as passivation layer 210,may be deposited upon a GaN material system heterostructure using lowpressure chemical vapor deposition (LPCVD) following mesa formation. Forexample, a heterostructure including layers 20-50 may be obtained viaconventional commercial sources. Applying the passivation prior to ohmiccontact and T-gate metallization processing allows the formation of ahigher temperature/denser passivation layer, and allows passivationunder the T-Gate extensions which is not the case for post gatepassivation as shown in FIG. 1 region 110. The heterostructure, orwafer, may be cleaned, such as by using acetone, methanol andisopropanol dips. The wafer may then be rinsed and spin dried. Furthercleaning, including a buffered oxide etch (BOE) and/or HF bath may alsobe used. The cleaned wafer may again be rinsed and dried. The cleanedwafer may then be subjected to a LPCVD process using NH₃ and SiH₂Cl₂gases flowed at about 70 and 30 standard cubic centimeters per second(sccm) at about 765 degrees Celsius (deg. C.) and 370-460 millitorr (mT)to deposit SiNx. Processing time may be appropriate for depositing adense nitride passivation layer having a thickness of between about 450and 2000 angstroms, for example. Passivation layer 210 may be suitablefor use with a wide-variety of GaN material system based HEMTs.

Referring now also to FIG. 3, there is shown a doped channel HEMT 300according to an aspect of the present invention. Again, like numeralsrefer to like elements of the invention. HEMT 300 includes a dopedchannel 310. Channel 310 may include doped GaN or InGaN, by way ofnon-limiting example. Channel 310 may be between about 50 angstroms and200 angstroms thick, and preferably about 100 angstroms, where barrierlayer 50 is around 100 angstroms to 500 angstroms thick, and preferablyabout 200-300 angstroms thick. HEMT 300 may exhibit improved performanceat high temperatures. Channel 310 may be n-type Si doped on the order ofabout 1016 to 1018 cm⁻³. Channel 310 may be substantially uniformlydoped. Layer 310 may be grown upon buffer layer 40. HEMT 300 performancemay be relatively temperature independent, as compared with HEMT 10 or200. This may result from the scattering mechanism being dominated inthe doped channel 310 by impurity scattering, which is relativelytemperature independent.

Referring now also to FIG. 4, there is shown a diagrammatic view of anHEMT 400 with implanted source and drain regions 410S, 410D,respectively, according to an aspect of the present invention. Again,like references refer to like elements of the invention. Source/drainimplantation may serve to greatly increase conductivity under the sourceand drain metal electrodes, thus facilitating low contact resistances.Implanted regions 410S, 410D may be combined with a doped channel, suchas channel 310 of FIG. 3. Implanted regions 410S, 410D may also beparticularly well suited for use with a relatively thin, undoped AlNsub-barrier layer—which may otherwise hinder providing good, lowresistance ohmic contacts. Aspects of forming implanted source and drainregions are detailed with respect to FIGS. 11A-11E.

Referring now also to FIG. 5, there is shown a diagrammatic view of anHEMT 500 incorporating an AlN sub-barrier layer 510 according to anaspect of the present invention. Again, like references refer to likeelements. Layer 510 may be relatively thin, on the order of about 10-20angstroms, and be composed of undoped AlN. Layer 510 may serve toenhance the charge in the 2DEG channel 60 and reduce the noise figure inHEMT 500. Again, layer 510 may be incorporated with a doped channel,such as channel 310 of FIG. 3, and/or implanted source and drainregions, such as regions 410S and 410D of FIG. 4.

Referring now also to FIG. 6, there is shown a diagrammatic view of adouble heterostructure HEMT 600 according to an aspect of the presentinvention. Again, like references designate like elements of theinvention. HEMT 600 includes a channel layer 610. Channel 610 may takethe form of un-doped GaN or InGaN, by way of non-limiting example only.In such an embodiment, HEMT 600 takes the form of an AlGaN/(ln)GaN/AlGaNdouble heterostructure HEMT to provide a better carrier confinement inthe channel 610. Channel 610 may be around 50 angstroms to 200 angstromsthick, preferably about 100 angstroms, where layer 50 is around 100angstroms to 500 angstroms thick and preferably about 200-300 angstromsthick. Layer 620 may be undoped, or doped with Fe or other elements toprovide semi-insulating properties. Layer 620 may be about 50 angstromsto 5000 angstroms thick, preferably about 100-500 angstroms.

Referring now also to FIG. 7, there are shown some characteristics of adouble heterostructure HEMT, such as HEMT 600 of FIG. 6, and a singleheterostructure HEMT. As is shown therein, a double heterostructure HEMTmay exhibit a higher channel mobility compared to other HEMT structures.Also, a double heterostructure HEMT may exhibit a lower 2DEG sheetdensity as compared to other HEMT structures.

According to an aspect of the present invention, an HEMT device, such asany of devices 10, 200, 300, 400, 500 and 600 may be formed into devicesincluding sloped mesas. The shaping of HEMT devices to include a slopedmesa may better isolate such devices, improve device manufacturingyields, and improve long-term device reliability, for example. Referringnow to FIG. 8, there is shown a device 800 according to an aspect of thepresent invention. As will be understood by those possessing an ordinaryskill in the pertinent arts, the structure of illustrated device 800largely corresponds to a mesa structure of device 400 for non-limitingpurposes of illustration only. Device 800 includes a sloped mesa. Again,like references identify like elements of the invention. Gate 80, drain90 and source 100 are positioned on the mesa plateau portion 810 oflayer 50. The mesa etch may terminate in the GaN Buffer layer 40, andhave a MESA etch depth of about 2000 angstroms compared to a barrierlayer 50 thickness of about 200 angstroms.

According to an aspect of the present invention, GaN material systemheterostructures may be formed into mesa-formed HEMT devices with theassistance of one or more protecting layers to minimize the potential ofsurface damage to the sensitive barrier layer. A GaN material systemheterostructure suitable for use may take the form of a wafer having alayer structure consistent with any one of structures 200-600, absentpassivation layers, gates, sources and drains, for example.

Referring now also to FIGS. 9A-9D, there are shown structures 900A-900Dat various processing steps according to an aspect of the presentinvention. Prior to processing, a GaN material system heterostructurewafer, hereinafter referred to simply as a wafer, may be cleaned usingacetone, methanol and isopropyl alcohol dips, and subsequent rinsing andspin drying, for example. According to an aspect of the presentinvention, a dielectric film may be used to mitigate photo resistremoval damage that may otherwise occur during mesa formation. Referringfirst to FIG. 9A, there is shown a structure 900A. Illustrated structure900A includes an AlGaN/GaN heterostructure 910. Such a structure isanalogous to that shown in FIGS. 1-6, absent T-gate 80, source 90, drain100 and passivation layer 70, 210. Dielectric film 920 may be lowtemperature chemical vapor deposited oxide (PECVD or Low temperature CVDdeposited) over structure 910. Film 920 may take the form of a thinlayer (about 1000 angstroms or less) of silicon dioxide (Si0₂), forexample.

Oxide film 920 may be formed by flowing SiH₄ and O₂ at rates of about 43sccm and 90 sccm, respectively, at a pressure of about 260 mT and atemperature of about 440 deg. C. Film 920 may serve as a protectionlayer for the AlGaN barrier surface during mesa etching and subsequentetch mask removal. Temperatures may rise significantly during mesaetching resulting in hardening of the resist masking layer 930 (FIG.9B). This may render the photo resist on the structure difficult toremove. Layer 920 protects the barrier layer surface during resistremoval, and thus facilitates plasma ashing to remove photoresist fromstructure 910. Direct exposure of the AlGaN barrier to plasma ashing hasbeen shown to damage the barrier layer and reduce or remove the 2DEG inthe channel.

Referring now also to FIG. 9B, there is shown a structure 900B.Structure 900B additionally includes a patterned photoresist layer 930.Layer 930 may be composed of a commercially available photoresist, suchas AZ4400 available from Shipley, for example. Layer 930 may bepatterned in the form of a mesa mask using conventional methodologies,such as spin coating, exposing, developing and reflowing, for example.

Referring now also to FIG. 9C, the patterned mask layer 930 may besuitable for facilitating shaping of layer 920 and structure 910 into amesa structure 900C. For example, a reactive ion etch (RIE) may be usedto remove portions of layer 920 dependently upon mask layer 930. A GaNlayer within structure 910 may serve as an etch stop for a NF₃/Ar etchflowed at about 12/28 sccm, respectively, at about 100 mT and 400 watts(W) using a carbon plate. Referring still to structure 900C, a dilutedoxide etch, such as an etch using a diluted HF etchant, may then be usedto clean the GaN surface exposed by the reactive ion etch. Referringstill to structure 900C, a high density, Inductively Coupled Plasma(ICP) etch may be used to form the GaN layer into the desired mesashape. BCl₃ and Cl₂ gases may be flowed at rates of 10 sccm and 30 sccmduring ignition and 15 sccm and 30 sccm during etching, respectively. RFpower used may be around 50 W and 300 W during ignition and 15 W (usinga 90 v bias) and 300 W during etching. The etching may be carried out ataround 5 mT and about 10 deg. C. Etch depth can range from 1000-3000Angstroms, for example.

Referring now also to FIG. 9D, patterned layer 930 and the remainingportions of layer 920 may then be selectively removed to provide mesashaped structure 900D. For example, an O₂ ashing or descum process maybe carried out to remove densified resist. Processing may include anacetone bath and propanol rinse. Another ashing or descum process maythen be effected, to better ensure all resist has been removed.Dielectric layer 920 remains over the barrier layer for protectionduring this removal step. A wet oxide etch may then be used to removethe remaining layer 920. A dilute HF etchant (such as on the order ofabout 1:20) may be used at room temperature. The mesa shaped wafer maythen again be cleaned, such as by using a photo resist stripping bath,for example. The use of layer 920 may serve to protect the relativelyfragile channel area of structure 910 during the aforementionedprocessing over which the gate, and source and drain electrodes will beformed.

Structure 900D may be provided with a T-gate 80, source 90, drain 100and passivation layer 210 to provide a device analogous to device 800 ofFIG. 8, for example—absent doped regions.

Referring now also to FIGS. 10A-10C, according to an aspect of thepresent invention, ohmic contact openings for the source and drainregions may be plasma treated prior to ohmic contact metallization. AnHEMT structure to be plasma treated in accordance with the presentinvention may take the form of one of structures 100-600 of FIGS. 1-6,or 800 of FIG. 8. Plasma treating AlGaN/GaN heterostructure ohmiccontact openings immediately prior to ohmic contact metallization maylower the ohmic contact resistance by creating a near-surface conductinglayer with N-vacancies. It may also serve to clean the structure priorto contact metallization. It may also improve the ohmic metal surfacemorphology after Rapid Thermal Annealing (RTA) by creating microscopicsurface features. Illustrated structure 1000A includes an AlGaN/GaNheterostructure 1010, such as a structure analogous to structure 900Dshown in FIG. 9D (only the mesa plateau is shown). Illustrated structure1000A also includes a surface passivating layer 1020. Layer 1020 maytake the form of a SiNx layer that has been formed over heterostructure1010 using high temperature, densified LPCVD, as in one of structures100-600 of FIGS. 1-6, or 800 of FIG. 8. Layer 1020 may also be formedusing plasma enhanced chemical vapor deposition (PECVD), or evaporation,for example. Layer 1020 may take the form of an AlN film formed onstructure 1010 using molecular beam expitaxy (MBE) or sputtering, Sc₂O₃,MgO using MBE, or SiO₂ using LPCVD or PECVD. Layer 1020 may take theform of a combination of these layers as well, for example.

Referring now also to FIG. 10B, structure 1000B includes a patternedphotoresist layer 1030 over protection or passivation layer 1020. Layer1030 may have openings 1040, 1050 corresponding to ohmic contact regionsto layer 1010, such as those corresponding to source 90 and/or drain 100(FIG. 8), for example. Structure 1000B may be subjected to a selectiveetch well suited for removing portions of layer 1020 exposed by openings1040, 1050 in layer 1030. For example, structure 1000B may be subjectedto a wet etch such as dilute HF or buffered oxide etch (BOE). A plasmaetch may also be used for etching. Layer 1020, which may be akin tolayer 210 and take the form of a dense SiN_(x), may be etched using aninductivety coupled plasma (ICP) etch, for example. SF₆ gas may beflowed at rates of 30 sccm during ignition and etching. RF powers usedmay be around 50 W and 600 W during ignition and 5 W and 600 W duringetching. The etching may be carried out at around 20 mT and at about 10deg. C. The resulting structure 1000C of FIG. 10C may then be subjectedto an ICP etch prior to ohmic contact metallization deposition. This ICPetch may be selected to remove less than around 50 angstroms of thebarrier layer of the heterostructure 1010, to better ensure an ohmiccontact formation during metallization deposition and anneal. BCl₃ andCl₂ gases may be flowed at rates of 15 and 30 sccm, and RF power usedmay be around 40 W. The etch may be carried out for about 20-60 secondsat around 5 mTorr. at about 10 deg. C. N₂ gas may also be used at flowrates of 15 sccm. RF powers used may be around 40 W for RF source and300 W for ICP source. The etch may be carried out for about 30-60seconds at around 3 mTorr. at about 10 deg.

Referring now also to FIG. 10C, regions 1060, 1070 may have N-vacanciescreated in heterostructure 1010 by the ICP etch treatment. Regions 1060,1070 of structure 1010 correspond to openings 1040, 1050. Regions 1060,1070 may correspond to ohmic contact regions for source and drainelectrodes providing for improved device performance due to reducedohmic contact resistances for source and drain electrodes. Photo resist1030 may be removed analogously to the photo resist removal discussedwith regard to FIGS. 9A-9D. Remaining portions of layer 1020 may beutilized as surface passivation, analogous to layer 210 of FIG. 4, orthe layer may be removed and replaced. Alternatively, one or more oflayers 1020, 1030 may be used as a lift off material for one or moremetallization layers deposited to form ohmic contacts for the source anddrain electrodes (e.g. layer 1195 of FIG. 11D). For example, standardTi—Al—Ti—Au, Ti—Al—Mo—Au, Ti—Al—Ni—Au, or Ti—Al—Pt—Au metallizationstacks may be used. After ICP pre-cleaning, an optional pre-ohmiccontact metal deposition cleaning of the exposed portions of regions1060 and 1070 may be used to insure any native oxide is removed. Forexample, O₂ ashing and a wet diluted and buffered oxide etch may beused. As will be understood by those possessing an ordinary skill in thepertinent arts, an RTA anneal at between 750 deg. C. and 850 deg. C. maybe performed following ohmic contact metal liftoff processing tocomplete the formation of the ohmic contacts.

Referring now also to FIG. 11A, structure 1100A is akin to structure1000B of FIG. 10B. A further embodiment to reduce source drainresistance is to ion implant the source and drain regions prior to ohmiccontact formation. Such a method may implant Si⁺ or Ge⁺ or co-implantSi⁺ and N⁺ or Ge⁺ and N⁺ into portions of the heterostructure 1110exposed through openings 1140 and 1150 in FIG. 11B formed in ananalogous fashion to openings 1040 and 1050 in FIG. 10C. Layer 1130 maybe a thick photoresist or a metal mask to block the implant. Layer 1120may take the form of AlN to facilitate protection of the AlGaN/GaNheterostructure from damage during implant annealing. Implanted regions1160 and 1170 in FIG. 11C may be thermally activated between about 1000deg. C. and 1300 deg. C. with an AlN mask. The photoresist or metal maskmay be removed from the wafer prior to annealing. According to an aspectof the present invention, RTA may be used to activate the dopant.Referring now also to FIG. 11C, the AlN anneal protection layer may beretained as the pasivation layer, or it may be removed and replaced byLPCVD silicon nitride.

Referring now also to FIGS. 11D and 11E, ohmic contacts to layer 1110through openings 1140, 1150 in passivation layer 1120 corresponding tosource and drain implanted regions may be provided. A photo resist layer1130 may be reapplied over passivation layer 1120, analogously to thephoto resist layers discussed hereinabove. Photo resist layer 1130 maybe patterned to reopen openings in passivation layer 1020 correspondingto previously implanted source and drain regions. Passivation layer 1020openings are then ready for removal of the AlN to the AlGaN/GaNHeterostructure surface. The exposed portions of the 1110 surface (ohmiccontact openings) may be cleaned followed by ohmic contact metaldeposition, liftoff processing and annealing as discussed previously.Standard liftoff lithography and metallization steps may be then used toprovide source and drain electrodes 1192 and 1194 shown in FIG. 11E. Forexample, a Ti—Ni—Au source/drain metallization may be used.

The resulting device 1100E may include a heterostructure 1110 includingdoped regions 1160, 1170, and passivation layer 1120, and be largelyanalogous to the form of device 400 of FIG. 4 or 800 of FIG. 8, absentohmic contacts and source, drain and gate metallization, by way ofnon-limiting example only.

Referring now also to FIGS. 12A-12D, there are shown structures1200A-1200D that represent various processing steps according to anaspect of the present invention. Structure 1200D may take the form of aHEMT according to an aspect of the present invention, including drainand source electrodes 1192, 1194 (that may be akin to drain and source90, 100 of FIG. 2), and a gate electrode 1298 (that may be akin to gate80 of FIG. 2). Structure 1200A of FIG. 12A may be analogous to structure1100A of FIG. 11A, but in this case the opening in the photo resist isin the gate metallization region. Photo resist layer 1230 may take theform of a PMMA, for example. Layer 1230 may take the form of a 495 PMMA,for example. Layer 1230 may be spin coated onto structure 1100E, forexample. Layer 1230 may be well suited for use as a processing mask forgate dielectric opening and gate electrode 1298 liftoff formation, forexample.

Referring now to FIG. 12A, an opening 1295 may be formed in layer 1230by e-beam exposure and developing as is shown in structure 1200A. Theposition and dimensions of opening 1295 may largely correspond to theposition and footprint dimensions of gate 1298 through passivation layer1120. Developer utilized may include MIBK:IPA. A developer may also beused to remove remaining portions of PMMA layer 1230. Referring now alsoto FIG. 12B, as shown in structure 1200B, etching may be used to removeportions of layer 1120 corresponding to opening 1295. A reactive ionetch (RIE) may be used for example. A PT-72 RIE machine may be operatedat about 0.04 mT, with a flow of 70 sccm CF₄ at about 150 W. The barriersurface 1296 exposed in FIG. 12B is sensitive to RIE exposure and suchexposure can reduce the 2DEG in the channel. The RIE conditions may beselected to minimize 2DEG reduction. In addition, a rapid thermal anneal(RTA) process may be used to remove the ion damage from RIE plasma etch.

Referring now also to FIG. 12C, a PMMA has been reapplied to the waferin structure 1200C such that the post develop opening 1297 overlaps thegate footprint opening 1296. Gate metal deposition and subsequentliftoff processing may be used, resulting in the HEMT structure 1200Dshown in FIG. 12D. The preferred gate metallization is Ni/Pt/Au, with atotal thickness of between about 0.4 and 0.8 μm.

While the foregoing invention has been described with reference to theabove, various modifications and changes can be made without departingfrom the spirit of the invention. Accordingly, all such modificationsand changes are considered to be within the scope of the appendedclaims.

1-6. (canceled)
 7. A high electron mobility transistor comprising: a GaN material system based heterostructure; a passivating nitride layer over said heterostructure and defining a plurality of openings; a plurality of electrical contacts for said heterostructure and being formed through said openings; and a gate contact being formed through one of said openings and in contact with the GaN material system based heterostructure, wherein a portion of said passivating nitride layer is under a portion of the gate contact.
 8. The transistor of claim 7, wherein said electrical contacts comprise source and drain contacts comprising one of: Ti—Al—Ti—Au, Ti—Al—Mo—Au, Ti—Al—Ni—Au, or Ti—Al—Pt—Au, and a gate contact comprising one of: Ni/Pt/Au, Ni/Au, Pt/Au, or Ir/Au.
 9. The transistor of claim 7, wherein said passivating nitride layer has a thickness between about 450 and 2000 angstroms. 10-15. (canceled)
 16. A high electron mobility transistor comprising: a mesa structure having a plateau and formed by a method comprising: providing a dielectric film over a GaN material system based heterostructure; providing a photo resist mask over said dielectric film; etching said dielectric film and heterostructure dependently upon said photo resist mask into a mesa structure; and removing said photo resist mask and remaining portions of said dielectric film; a passivating nitride layer over said plateau and defining at least one opening; and a gate contact extending through said opening and in contact with the GaN material system based heterostructure, wherein a portion of said passivating nitride layer is under at least one portion of said gate contact.
 17. The transistor of claim 16, wherein said etching comprises reactive ion etching said dielectric film and inductive coupled plasma etching said heterostructure.
 18. (canceled)
 19. The transistor of claim 16, wherein said GaN material system based heterostructure comprises an AlGaN/GaN double heterostructure. 20-21. (canceled)
 22. A high electron mobility transistor comprising: a GaN material system based heterostructure; doped source and drain contact regions for the GaN material system based heterostructure, wherein said doped source and drain contact regions are doped with at least one of Si+, Ge+, Si+ and N+, or Ge+ and N+; a passivating layer over said GaN material system based heterostructure; and a gate contact region in contact with the GaN material system based heterostructure, wherein a portion of said passivating nitride layer is under at least one portion of said gate contact.
 23. The transistor of claim 22, further comprising thermally activating said dopant in said heterostructure.
 24. The transistor of claim 22, further comprising forming contact electrodes over said dopant in said heterostructure.
 25. The transistor of claim 22, wherein said GaN material system based heterostructure comprises at least one AlGaN/GaN heterostructure.
 26. The transistor of claim 22, wherein said GaN material system based heterostructure comprises a dense nitride passivation layer.
 27. The transistor of claim 22, wherein said GaN material system based heterostructure comprises a doped channel.
 28. The transistor of claim 22, wherein said GaN material system based heterostructure comprises at least one AlGaN/GaN heterostructure further comprising an AlN layer.
 29. The transistor of claim 22, wherein said GaN material system based heterostructure comprises a double AlGaN/GaN heterostructure.
 30. The transistor of claim 22, wherein said GaN material system based heterostructure comprises a mesa region having gate, drain and source electrodes formed thereon.
 31. The transistor of claim 22, further comprising a mesa structure having a plateau, wherein said passivating layer is over said plateau.
 32. A high electron mobility transistor comprising: a GaN material system based heterostructure; doped source and drain contact regions for the GaN material system based heterostructure, wherein said doped source and drain contact regions are doped with at least one of Si+, Ge+, Si+ and N+, or Ge+ and N+; a passivating layer over said GaN material system based heterostructure; a channel laterally extending between the source and drain contact regions; and, a gate electrode having a portion extending through the passivating layer, the gate electrode having an overall width less than the width of the laterally extending channel.
 33. The transistor of claim 32, further comprising a mesa structure having a plateau, wherein said passivating layer is over said plateau. 